A flash or block erase memory (flash memory), such as, Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide Semiconductor (MOS) memory cells that are field effect transistors (FETs). Each FET, or flash, memory cell includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. The flash memory cell provides for nonvolatile data storage.
A typical configuration of a flash memory cell consists of a thin, high-quality tunnel oxide layer sandwiched between a conducting polysilicon floating gate and a crystalline silicon semiconductor substrate. The tunnel oxide layer is typically composed of silicon oxide (SixOy). The substrate includes a source region and a drain region that can be separated by an underlying channel region. A control gate is provided adjacent to the floating gate, and is separated by an interpoly dielectric. Typically, the interpoly dielectric can be composed of an oxide-nitride-oxide (ONO) structure.
A typical configuration of an array of flash memory cells includes rows and columns of flash memory cells. The array is supported by word lines and bit lines, wherein the word lines are coupled to gates of flash memory cells, and the bit lines are coupled to drains. The sources of the flash memory cells are commonly coupled together.
The flash memory cell stores data by holding charge within the floating gate. In a write or program operation, charge can be placed on the floating gate through hot electron injection, or Fowler-Nordheim (F-N) tunneling. In addition, F-N tunneling can be typically used for erasing the flash memory cell through the removal of charge on the floating gate.
Prior Art FIG. 1 is a diagram of an exemplary MOSFET transistor 100 used as a flash memory device. Prior Art FIG. 1 illustrates the negative effects of punch-through due to reduced gate lengths. The MOSFET 100 includes a substrate 110 that includes a source region 140 and a drain region 170 that is separated by an underlying channel region under the stacked gate structure 120. The source region 140 intrudes under the gate stack 120. The drain region 170 also intrudes under the gate stack 120. These intrusions shorten the effective channel length between the source region 140 and the drain region 170.
As flash memory technology progresses, emphasis is directed to reduce the size of the memory cells in the flash memory. However, continued reduction in size of the gate length of the MOSFET has been limited by short channel effects. Specifically, the behavior of the transistor is negatively governed by punch-through of electrons at the higher voltages. When the effective channel length between the source region 140 and the drain region 170 becomes too short, the depletion region under the gate stack 120 is formed partly by the bias voltage on the drain region 170 and the built-in potential of the source region 140. As a result, the depletion region 180 due to the bias voltage on the drain region 170 can extend to the depletion region 150 surrounding the source region 140.
Correspondingly, the barrier for electron injection from the source region 140 to the drain region 170 decreases due to the extension of the depletion region 180. Specifically, at positive drain voltages, the effective energy barrier height for electrons can be reduced resulting in electrons migrating from the source region 140 to the drain region 170. This is known as drain induced barrier lowering (DIBL).
In the worst case, when the depletion regions 180 and 150 touch each other punch-through will occur. This will result in loss of gate control over the channel, and result in significant current flow from the source 140 to the drain 170.
Thus, even when the MOSFET 100 is turned off by biasing the stacked gate to zero volts, for voltages that are applied to the drain region 170, an unwanted current can flow from the source region 140 to the drain region 170 due to punch-through. This in turn reduces the breakdown voltage of the MOSFET 100.
What is needed is an apparatus and method for reducing short channel effects in flash memory cells.